The present invention relates generally to electronic circuits, and more particularly to transconductance cell (or gm cell) based control loops such as phase locked loops, frequency locked loops, delay locked loops, combinations thereof (e.g., phase and frequency locked loops), and systems using the same.
As one type of control loop, a phase locked loop (PLL) is commonly used in many electronics applications to maintain a fixed phase relationship between an input (e.g., clock) signal and a reference signal. A phase locked loop designed for a digital application typically includes a phase and/or frequency detector, a charge pump, a loop filter, a VCO, and an (optional) divider. The phase detector determines the phase differences between an input signal (i.e., an input data stream or an input clock) and a reference signal derived from the VCO, and generates a detector output signal indicative of the detected phase differences. The charge pump receives the detector output signal and generates a set of phase error signals (e.g., UP and DOWN). The loop filter filters the phase error signals to generate a control signal that is then used to adjust the frequency of the VCO such that the frequencies of the two signals provided to the phase detector are locked.
FIG. 1 is a block diagram of a conventional phase locked loop 100. An input signal is provided to a phase detector 110 that also receives a reference signal from a divider 124. The input signal can be a clock signal, a data stream, or some other types of signal having phase and/or frequency information to which the phase locked loop can locked. The reference signal is typically a clock signal used to trigger the phase detector. Phase detector 110 generates an output signal PDOUT indicative of the timing differences (i.e., the phase differences) between the input signal and the reference signal. The PDOUT signal is provided to a charge pump 114 that generates an output signal CPOUT indicative of the detected phase error between the input and reference signals. In some designs, the CPOUT signal is logic high if the phase of the input signal is early (or late) relative to that of the reference signal, logic low if the phase of the input signal is late (or early) relative to that of the reference signal, and tri-stated for a period of time between clock edges.
The CPOUT signal is provided to a loop filter 120 that filters the signal with a particular transfer characteristic to generate a control signal. The control signal is then provided to, and used to control the frequency of, a voltage-controlled oscillator (VCO) 122. VCO 122 generates an output clock CLK_OUT having a frequency that is locked to that of the input signal (when the phase locked loop is locked). The output clock is provided to divider 124 that divides the frequency of the output clock by a factor of N to generate the reference signal. Divider 124 is optional and not used when the frequency of the output clock is the same as that of the input signal (i.e., N=1). The control signal adjusts the frequency of VCO 122 such that the frequencies of the two signals provided to phase detector 110 are locked.
The charge pump typically requires an input signal having rail-to-rail signal swing and sharp edges. Signals meeting these requirements can be readily provided by a phase detector at (relatively) low operating frequencies. However, at higher frequencies (e.g., 2.488 GHz for a SONET OC-48 transceiver), it is difficult to design a phase detector having rail-to-rail signal swing and sharp edges. To provide the required signal characteristics, the phase detector would typically need to be designed using a combination of large die area and large amounts of bias current. Besides the design challenge for such phase detector, the rail-to-rail signal swing and sharp edges generate large amounts of noise that can degrade the performance of the phase locked loop and other nearby circuits.
Accordingly, locked loops capable of high speed of operation and having improved performance are highly desirable.
The invention provides transconductance (or gm) cell based control loops that can be advantageously used in many applications, especially high speed communications systems. The gm cell (or gm amplifier) operates on signals having smaller swings (e.g., 400 mV peak-to-peak or smaller) and more gradual transition edges. These signal characteristics allow the preceding phase detector to be designed to operate at high frequencies and biased with less current. The gm cell based locked loops of the present invention can be efficiently designed and fabricated, and also have improved performance (e.g., reduced clock jitter) over conventional locked loops.
An embodiment of the invention provides a locked loop for use in a high frequency application such as an optical transceiver. The locked loop includes a detector, a transconductance (gm) amplifier, a loop filter, and an oscillator. The detector (which can be a phase detector or a frequency detector, or combination of both) receives an input signal and a reference signal and provides a detector output signal indicative of the difference between the input and reference signals. The difference can be phase or frequency, etc., depending on the application. The gm amplifier receives and converts the detector output signal to a current signal. The loop filter receives and filters the current signal with a particular transfer function to provide a control signal. The oscillator receives the control signal and provides an oscillator signal (e.g., a clock) having a property (e.g., frequency) that is adjusted by the control signal. The reference signal is adjusted by from the oscillator signal.
In one design, the gm amplifier includes a differential amplifier coupled to a current load circuit and a common mode feedback circuit. The differential amplifier receives the detector output signal and provides signal gain, the current load circuit provides the current load for the differential amplifier, and the common mode feedback circuit provides a bias control signal that adjusts the average current of the current load.
The locked loop typically includes a lowpass filter that receives and filters the detector output signal to remove high frequency components. The filtered signal is then provided to the gm amplifier. The lowpass filter can be implemented as a single-pole RC filter. In some designs, the locked loop further includes a divider that receives and divides the frequency of the oscillator signal by a factor of N to generate the reference signal. The input signal can be a serial data stream or a clock signal. For optical applications, the serial data stream can have a data rate of 2.488 GHz or higher.
The detector and gm amplifier can be implemented using CMOS circuits. For improved performance (e.g., improved linearity, higher immunity to noise, and so on), the elements of the locked loop (e.g., the detector, the gm amplifier, and others) can be implemented using differential circuits and designed to operate on differential signals. The detector, gm amplifier, and at least a portion of the loop filter and oscillator can be fabricated on one CMOS integrated circuit. The detector output signal can be designed to have a peak-to-peak signal swing of less than one volt (e.g., 400 mV peak-to-peak in one specific design).
Another embodiment of the invention provides a method for generating an oscillator signal that is locked to an input signal. In accordance with the method, the input signal and a reference signal derived from the oscillator signal are received and used to generate a detector output signal indicative of the timing differences between the input and reference signals. The detector output signal is converted to a current signal with a gm amplifier and filtered with a loop filter to generate a control signal. The frequency of an oscillator is then adjusted with the control signal such that the oscillator signal is locked to the input signal. The detector output signal is typically filtered with a lowpass filter to remove high frequency components. The input signal can be a serial data stream or a clock signal, and the detector output signal can have a peak-to-peak signal swing of less than one volt. Other features such as those described above can also be applied.